1. Field of the Invention
The present invention pertains to the field of semiconductor processing. More particularly, this invention relates to the formation narrow spaces.
2. Background of the Related Art
Metal oxide semiconductor (MOS) technology is used to form a number of different types of devices including memory devices and microprocessors. The basic device structure forming the field effect transistor (FET) comprises an insulated gate electrically overlaying a channel region between a source and drain. The gate is an electrically conductive material separated a small distance from the underlying silicon substrate via a thin insulating layer usually made of silicon oxide. The source and drain are formed in the silicon substrate by introducing dopants in controlled amounts to make the source and drain n-type or p-type relative to the surrounding silicon. The dopants for the source and drain are inserted into the silicon using diffusion or ion implantation, both processes which require subjecting the substrate to high temperatures.
Early transistor structures were formed by first diffusing dopants into the source and drain regions and afterward forming the gate. The formation of the gate was done by depositing gate material and subsequently doing conventional photolithography patterning. Because of the need to ensure that the gate overlay the entire channel region and limitations in manufacturing tolerances, high volume manufacturing required a significant gate overlap into the source and drain to ensure that the gate adequately covered the entire channel region. For smaller device sizes the gate overlap led to significant parasitic capacitance between the gate and source region and the gate and drain region. A self-aligning manufacturing process was then developed whereby the gate itself would serve as a mask for forming the source and drain. The gate had to be formed first, so that the source and drain could be formed in alignment with the gate. A consequence of the self-aligned process was that the gate material had to be changed from metal to silicon because of the requirement that the gate withstand the high temperature processing for forming the source and drain.
In an effort to achieve smaller than 100 nm gate lengths, a process was developed whereby conventional photolithography is used to define edges onto which the dimensions of the future gate is established. This process is referred to as "litho-less". The litho-less process provides for greater critical dimension control and allows for the formation of very small devices, which in turn provides greater device performance. An example of this process is shown in FIGS. 1a-1k. FIG. 1a shows a silicon substrate 130. A layer of gate dielectric 120, comprising silicon oxide, is formed on the substrate 130. A layer of polycrystalline silicon (polysilicon) 110 is formed on the gate dielectric 120. In FIG.1b, a layer of sacrificial oxide 140 is shown formed on the layer of polysilicon 110. The layer of sacrificial oxide 140 is patterned using a first mask 145 shown in FIG. 1c. The resulting intermediate structure showing the patterned sacrificial oxide 142 is depicted in FIG. 1d. A layer of silicon nitride 150 is formed, as shown in FIG. 1e. FIG. 1f discloses that the silicon nitride 150 is etched to create spacer 151. The sacrificial oxide 142 is removed, leaving spacer 151, as depicted in FIG. 1g. FIG. 1h shows that the exposed portion of the polysilicon 110 is removed. FIG. 1i indicates that the nitride spacer 151 is removed, exposing the remaining polysilicon 112, thus forming the transistor gate. The remainder of the transistor structure is formed using standard CMOS process.
A problem with the above litho-less process for forming a transistor gate is that it does not allow for channel engineering, since the gate serves to mask the channel region. Channel engineering techniques such as implantation and raised source/drain structures provide reduced short channel effect, resulting in greater device performance and increased reliability. Thus, what is desired is a method for forming a transistor gate using a litho-less technique that allows for channel engineering.
The above litho-less process allows for the formation of sub-lithographic gate lengths. Sub-lithographic gate lengths are those gate lengths that are not achievable using conventional photolithographic techniques, due to standard photolithographic resolution limits. Conventional photolithographic resolution limits are also encountered in the patterning of small or narrow spaces. Narrow spaces are used in every semiconductor product for transistor device active are definition and isolation. Thus, a method of forming narrow spaces using a litho-less process is also desirable.